		
VV (vdd 0) vsource type=dc dc=pvdd
		
parameters q=1.60218e-19 tox=1.85 eox=3.5e-20 k1=7.5 cox=eox/tox Ea=0.49 
parameters k=8.6174e-5 T0=10e-8 E01=0.08 eta1=0.9 eta2=0.5 delta=0.5
parameters t_stress=67487.798454 t_rec=18912.20154 tmp=353
parameters vd=1.1 vt=0.4

		
Va0 (anet0 0) vsource type=dc dc=0
Va1 (anet1 0) vsource type=dc dc=0
Va2 (anet2 0) vsource type=dc dc=0
Va3 (anet3 0) vsource type=dc dc=0
Va4 (anet4 0) vsource type=dc dc=0
Va5 (anet5 0) vsource type=dc dc=0
Va6 (anet6 0) vsource type=dc dc=0
Va7 (anet7 0) vsource type=dc dc=0
Va8 (anet8 0) vsource type=dc dc=0
Va9 (anet9 0) vsource type=dc dc=0
Va10 (anet10 0) vsource type=dc dc=0
Va11 (anet11 0) vsource type=dc dc=0
Va12 (anet12 0) vsource type=dc dc=0
Va13 (anet13 0) vsource type=dc dc=0
Va14 (anet14 0) vsource type=dc dc=0
Va15 (anet15 0) vsource type=dc dc=0
Va16 (anet16 0) vsource type=dc dc=0
Va17 (anet17 0) vsource type=dc dc=0
Va18 (anet18 0) vsource type=dc dc=0
Va19 (anet19 0) vsource type=dc dc=0
Va20 (anet20 0) vsource type=dc dc=0
Va21 (anet21 0) vsource type=dc dc=0
Va22 (anet22 0) vsource type=dc dc=0
Va23 (anet23 0) vsource type=dc dc=0
Va24 (anet24 0) vsource type=dc dc=0
Va25 (anet25 0) vsource type=dc dc=0
Va26 (anet26 0) vsource type=dc dc=0
Va27 (anet27 0) vsource type=dc dc=0
Va28 (anet28 0) vsource type=dc dc=0
Va29 (anet29 0) vsource type=dc dc=0
Va30 (anet30 0) vsource type=dc dc=0
Va31 (anet31 0) vsource type=dc dc=0

Vb0 (bnet0 0) vsource type=dc dc=0
Vb1 (bnet1 0) vsource type=dc dc=0.0
Vb2 (bnet2 0) vsource type=dc dc=0.0
Vb3 (bnet3 0) vsource type=dc dc=0.0
Vb4 (bnet4 0) vsource type=dc dc=0.0
Vb5 (bnet5 0) vsource type=dc dc=0.0
Vb6 (bnet6 0) vsource type=dc dc=0.0
Vb7 (bnet7 0) vsource type=dc dc=0.0
Vb8 (bnet8 0) vsource type=dc dc=0.0
Vb9 (bnet9 0) vsource type=dc dc=0.0
Vb10 (bnet10 0) vsource type=dc dc=0
Vb11 (bnet11 0) vsource type=dc dc=0
Vb12 (bnet12 0) vsource type=dc dc=0
Vb13 (bnet13 0) vsource type=dc dc=0
Vb14 (bnet14 0) vsource type=dc dc=0
Vb15 (bnet15 0) vsource type=dc dc=0
Vb16 (bnet16 0) vsource type=dc dc=0
Vb17 (bnet17 0) vsource type=dc dc=0
Vb18 (bnet18 0) vsource type=dc dc=0
Vb19 (bnet19 0) vsource type=dc dc=0
Vb20 (bnet20 0) vsource type=dc dc=0
Vb21 (bnet21 0) vsource type=dc dc=0
Vb22 (bnet22 0) vsource type=dc dc=0
Vb23 (bnet23 0) vsource type=dc dc=0
Vb24 (bnet24 0) vsource type=dc dc=0
Vb25 (bnet25 0) vsource type=dc dc=0
Vb26 (bnet26 0) vsource type=dc dc=0
Vb27 (bnet27 0) vsource type=dc dc=0
Vb28 (bnet28 0) vsource type=dc dc=0
Vb29 (bnet29 0) vsource type=dc dc=0
Vb30 (bnet30 0) vsource type=dc dc=0
Vb31 (bnet31 0) vsource type=dc dc=0
		
C0 (snet0 0) capacitor c=10f m=1
C1 (snet1 0) capacitor c=10f m=1
C2 (snet2 0) capacitor c=10f m=1
C3 (snet3 0) capacitor c=10f m=1
C4 (snet4 0) capacitor c=10f m=1
C5 (snet5 0) capacitor c=10f m=1
C6 (snet6 0) capacitor c=10f m=1
C7 (snet7 0) capacitor c=10f m=1
C8 (snet8 0) capacitor c=10f m=1
C9 (snet9 0) capacitor c=10f m=1
C10 (snet10 0) capacitor c=10f m=1
C11 (snet11 0) capacitor c=10f m=1
C12 (snet12 0) capacitor c=10f m=1
C13 (snet13 0) capacitor c=10f m=1
C14 (snet14 0) capacitor c=10f m=1
C15 (snet15 0) capacitor c=10f m=1
C16 (snet16 0) capacitor c=10f m=1
C17 (snet17 0) capacitor c=10f m=1
C18 (snet18 0) capacitor c=10f m=1
C19 (snet19 0) capacitor c=10f m=1
C20 (snet20 0) capacitor c=10f m=1
C21 (snet21 0) capacitor c=10f m=1
C22 (snet22 0) capacitor c=10f m=1
C23 (snet23 0) capacitor c=10f m=1
C24 (snet24 0) capacitor c=10f m=1
C25 (snet25 0) capacitor c=10f m=1
C26 (snet26 0) capacitor c=10f m=1
C27 (snet27 0) capacitor c=10f m=1
C28 (snet28 0) capacitor c=10f m=1
C29 (snet29 0) capacitor c=10f m=1
C30 (snet30 0) capacitor c=10f m=1
C31 (snet31 0) capacitor c=10f m=1
		
KSA (anet0 anet1 anet2 anet3 anet4 anet5 anet6 anet7 anet8 anet9 anet10 anet11 anet12 anet13 anet14 anet15 anet16 anet17 anet18 \
     anet19 anet20 anet21 anet22 anet23 anet24 anet25 anet26 anet27 anet28 anet29 anet30 anet31 bnet0 bnet1 bnet2 bnet3 bnet4 bnet5 bnet6 bnet7 \
     bnet8 bnet9 bnet10 bnet11 bnet12 bnet13 bnet14 bnet15 bnet16 bnet17 bnet18 bnet19 bnet20 bnet21 bnet22 bnet23 bnet24 bnet25 bnet26 bnet27 \
     bnet28 bnet29 bnet30 bnet31 snet0 snet1 snet2 snet3 snet4 snet5 snet6 snet7 snet8 snet9 snet10 snet11 snet12 snet13 snet14 snet15 snet16 snet17 snet18 snet19 snet20 snet21 snet22 snet23 snet24 snet25 snet26 snet27 snet28 snet29 snet30 snet31 vdd 0 vdd) ADDER

// Library name: PDVS
// Cell name: adder
// View name: schematic
subckt ADDER a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 \
             a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 b0 b1 b2 b3 b4 b5 b6 b7 \
             b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 \
             b28 b29 b30 b31 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 \
             s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 VDD VSS PBULK

               Sum7_0 (g1_0 p1_0 s0 VDD VSS PBULK) FirstSum
               Sum7_1 (c_0 g1_1 p1_1 s1 VDD VSS PBULK) Sum
               Sum7_2 (c_1 g1_2 p1_2 s2 VDD VSS PBULK) Sum
               Sum7_3 (c_2 g1_3 p1_3 s3 VDD VSS PBULK) Sum
               Sum7_4 (c_3 g1_4 p1_4 s4 VDD VSS PBULK) Sum
               Sum7_5 (c_4 g1_5 p1_5 s5 VDD VSS PBULK) Sum
               Sum7_6 (c_5 g1_6 p1_6 s6 VDD VSS PBULK) Sum
               Sum7_7 (c_6 g1_7 p1_7 s7 VDD VSS PBULK) Sum
               Sum7_8 (c_7 g1_8 p1_8 s8 VDD VSS PBULK) Sum
               Sum7_9 (c_8 g1_9 p1_9 s9 VDD VSS PBULK) Sum
               Sum7_10 (c_9 g1_10 p1_10 s10 VDD VSS PBULK) Sum
               Sum7_11 (c_10 g1_11 p1_11 s11 VDD VSS PBULK) Sum
               Sum7_12 (c_11 g1_12 p1_12 s12 VDD VSS PBULK) Sum
               Sum7_13 (c_12 g1_13 p1_13 s13 VDD VSS PBULK) Sum
               Sum7_14 (c_13 g1_14 p1_14 s14 VDD VSS PBULK) Sum
               Sum7_15 (c_14 g1_15 p1_15 s15 VDD VSS PBULK) Sum
               Sum7_16 (c_15 g1_16 p1_16 s16 VDD VSS PBULK) Sum
               Sum7_17 (c_16 g1_17 p1_17 s17 VDD VSS PBULK) Sum
               Sum7_18 (c_17 g1_18 p1_18 s18 VDD VSS PBULK) Sum
               Sum7_19 (c_18 g1_19 p1_19 s19 VDD VSS PBULK) Sum
               Sum7_20 (c_19 g1_20 p1_20 s20 VDD VSS PBULK) Sum
               Sum7_21 (c_20 g1_21 p1_21 s21 VDD VSS PBULK) Sum
               Sum7_22 (c_21 g1_22 p1_22 s22 VDD VSS PBULK) Sum
               Sum7_23 (c_22 g1_23 p1_23 s23 VDD VSS PBULK) Sum
               Sum7_24 (c_23 g1_24 p1_24 s24 VDD VSS PBULK) Sum
               Sum7_25 (c_24 g1_25 p1_25 s25 VDD VSS PBULK) Sum
               Sum7_26 (c_25 g1_26 p1_26 s26 VDD VSS PBULK) Sum
               Sum7_27 (c_26 g1_27 p1_27 s27 VDD VSS PBULK) Sum
               Sum7_28 (c_27 g1_28 p1_28 s28 VDD VSS PBULK) Sum
               Sum7_29 (c_28 g1_29 p1_29 s29 VDD VSS PBULK) Sum
               Sum7_30 (c_29 g1_30 p1_30 s30 VDD VSS PBULK) Sum
               Sum7_31 (c_30 g1_31 p1_31 s31 VDD VSS PBULK) Sum

               WTriangle6_0 (c_0 g6_0 PBULK VDD VSS) WTriangle
               WTriangle6_1 (c_1 g6_1 PBULK VDD VSS) WTriangle
               WTriangle6_2 (c_2 g6_2 PBULK VDD VSS) WTriangle
               WTriangle6_3 (c_3 g6_3 PBULK VDD VSS) WTriangle
               WTriangle6_4 (c_4 g6_4 PBULK VDD VSS) WTriangle
               WTriangle6_5 (c_5 g6_5 PBULK VDD VSS) WTriangle
               WTriangle6_6 (c_6 g6_6 PBULK VDD VSS) WTriangle
               WTriangle6_7 (c_7 g6_7 PBULK VDD VSS) WTriangle
               WTriangle6_8 (c_8 g6_8 PBULK VDD VSS) WTriangle
               WTriangle6_9 (c_9 g6_9 PBULK VDD VSS) WTriangle
               WTriangle6_10 (c_10 g6_10 PBULK VDD VSS) WTriangle
               WTriangle6_11 (c_11 g6_11 PBULK VDD VSS) WTriangle
               WTriangle6_12 (c_12 g6_12 PBULK VDD VSS) WTriangle
               WTriangle6_13 (c_13 g6_13 PBULK VDD VSS) WTriangle
               WTriangle6_14 (c_14 g6_14 PBULK VDD VSS) WTriangle
               WTriangle6_15 (c_15 g6_15 PBULK VDD VSS) WTriangle
               WTriangle6_16 (c_16 g6_16 PBULK VDD VSS) WTriangle
               WTriangle6_17 (c_17 g6_17 PBULK VDD VSS) WTriangle
               WTriangle6_18 (c_18 g6_18 PBULK VDD VSS) WTriangle
               WTriangle6_19 (c_19 g6_19 PBULK VDD VSS) WTriangle
               WTriangle6_20 (c_20 g6_20 PBULK VDD VSS) WTriangle
               WTriangle6_21 (c_21 g6_21 PBULK VDD VSS) WTriangle
               WTriangle6_22 (c_22 g6_22 PBULK VDD VSS) WTriangle
               WTriangle6_23 (c_23 g6_23 PBULK VDD VSS) WTriangle
               WTriangle6_24 (c_24 g6_24 PBULK VDD VSS) WTriangle
               WTriangle6_25 (c_25 g6_25 PBULK VDD VSS) WTriangle
               WTriangle6_26 (c_26 g6_26 PBULK VDD VSS) WTriangle
               WTriangle6_27 (c_27 g6_27 PBULK VDD VSS) WTriangle
               WTriangle6_28 (c_28 g6_28 PBULK VDD VSS) WTriangle
               WTriangle6_29 (c_29 g6_29 PBULK VDD VSS) WTriangle
               WTriangle6_30 (c_30 g6_30 PBULK VDD VSS) WTriangle
               WTriangle6_31 (c_31 g6_31 PBULK VDD VSS) WTriangle

               WSquare5_0 (g5_0 g6_0 PBULK p5_0 p6_0 VDD VSS) WSquare
               WSquare5_1 (g5_1 g6_1 PBULK p5_1 p6_1 VDD VSS) WSquare
               WSquare5_2 (g5_2 g6_2 PBULK p5_2 p6_2 VDD VSS) WSquare
               WSquare5_3 (g5_3 g6_3 PBULK p5_3 p6_3 VDD VSS) WSquare
               WSquare5_4 (g5_4 g6_4 PBULK p5_4 p6_4 VDD VSS) WSquare
               WSquare5_5 (g5_5 g6_5 PBULK p5_5 p6_5 VDD VSS) WSquare
               WSquare5_6 (g5_6 g6_6 PBULK p5_6 p6_6 VDD VSS) WSquare
               WSquare5_7 (g5_7 g6_7 PBULK p5_7 p6_7 VDD VSS) WSquare
               WSquare5_8 (g5_8 g6_8 PBULK p5_8 p6_8 VDD VSS) WSquare
               WSquare5_9 (g5_9 g6_9 PBULK p5_9 p6_9 VDD VSS) WSquare
               WSquare5_10 (g5_10 g6_10 PBULK p5_10 p6_10 VDD VSS) WSquare
               WSquare5_11 (g5_11 g6_11 PBULK p5_11 p6_11 VDD VSS) WSquare
               WSquare5_12 (g5_12 g6_12 PBULK p5_12 p6_12 VDD VSS) WSquare
               WSquare5_13 (g5_13 g6_13 PBULK p5_13 p6_13 VDD VSS) WSquare
               WSquare5_14 (g5_14 g6_14 PBULK p5_14 p6_14 VDD VSS) WSquare
               WSquare5_15 (g5_15 g6_15 PBULK p5_15 p6_15 VDD VSS) WSquare
               BSquare5_16 (g5_16 g6_16 g5_0 PBULK p5_16 p6_16 p5_0 VDD VSS) BSquare
               BSquare5_17 (g5_17 g6_17 g5_1 PBULK p5_17 p6_17 p5_1 VDD VSS) BSquare
               BSquare5_18 (g5_18 g6_18 g5_2 PBULK p5_18 p6_18 p5_2 VDD VSS) BSquare
               BSquare5_19 (g5_19 g6_19 g5_3 PBULK p5_19 p6_19 p5_3 VDD VSS) BSquare
               BSquare5_20 (g5_20 g6_20 g5_4 PBULK p5_20 p6_20 p5_4 VDD VSS) BSquare
               BSquare5_21 (g5_21 g6_21 g5_5 PBULK p5_21 p6_21 p5_5 VDD VSS) BSquare
               BSquare5_22 (g5_22 g6_22 g5_6 PBULK p5_22 p6_22 p5_6 VDD VSS) BSquare
               BSquare5_23 (g5_23 g6_23 g5_7 PBULK p5_23 p6_23 p5_7 VDD VSS) BSquare
               BSquare5_24 (g5_24 g6_24 g5_8 PBULK p5_24 p6_24 p5_8 VDD VSS) BSquare
               BSquare5_25 (g5_25 g6_25 g5_9 PBULK p5_25 p6_25 p5_9 VDD VSS) BSquare
               BSquare5_26 (g5_26 g6_26 g5_10 PBULK p5_26 p6_26 p5_10 VDD VSS) BSquare
               BSquare5_27 (g5_27 g6_27 g5_11 PBULK p5_27 p6_27 p5_11 VDD VSS) BSquare
               BSquare5_28 (g5_28 g6_28 g5_12 PBULK p5_28 p6_28 p5_12 VDD VSS) BSquare
               BSquare5_29 (g5_29 g6_29 g5_13 PBULK p5_29 p6_29 p5_13 VDD VSS) BSquare
               BSquare5_30 (g5_30 g6_30 g5_14 PBULK p5_30 p6_30 p5_14 VDD VSS) BSquare
               BSquare5_31 (g5_31 g6_31 g5_15 PBULK p5_31 p6_31 p5_15 VDD VSS) BSquare

               WSquare4_0 (g4_0 g5_0 PBULK p4_0 p5_0 VDD VSS) WSquare
               WSquare4_1 (g4_1 g5_1 PBULK p4_1 p5_1 VDD VSS) WSquare
               WSquare4_2 (g4_2 g5_2 PBULK p4_2 p5_2 VDD VSS) WSquare
               WSquare4_3 (g4_3 g5_3 PBULK p4_3 p5_3 VDD VSS) WSquare
               WSquare4_4 (g4_4 g5_4 PBULK p4_4 p5_4 VDD VSS) WSquare
               WSquare4_5 (g4_5 g5_5 PBULK p4_5 p5_5 VDD VSS) WSquare
               WSquare4_6 (g4_6 g5_6 PBULK p4_6 p5_6 VDD VSS) WSquare
               WSquare4_7 (g4_7 g5_7 PBULK p4_7 p5_7 VDD VSS) WSquare
               BCircle4_8 (g4_8 g5_8 g4_0 PBULK p4_8 p5_8 p4_0 VDD VSS) BCircle
               BCircle4_9 (g4_9 g5_9 g4_1 PBULK p4_9 p5_9 p4_1 VDD VSS) BCircle
               BCircle4_10 (g4_10 g5_10 g4_2 PBULK p4_10 p5_10 p4_2 VDD VSS) BCircle
               BCircle4_11 (g4_11 g5_11 g4_3 PBULK p4_11 p5_11 p4_3 VDD VSS) BCircle
               BCircle4_12 (g4_12 g5_12 g4_4 PBULK p4_12 p5_12 p4_4 VDD VSS) BCircle
               BCircle4_13 (g4_13 g5_13 g4_5 PBULK p4_13 p5_13 p4_5 VDD VSS) BCircle
               BCircle4_14 (g4_14 g5_14 g4_6 PBULK p4_14 p5_14 p4_6 VDD VSS) BCircle
               BCircle4_15 (g4_15 g5_15 g4_7 PBULK p4_15 p5_15 p4_7 VDD VSS) BCircle
               BCircle4_16 (g4_16 g5_16 g4_8 PBULK p4_16 p5_16 p4_8 VDD VSS) BCircle
               BCircle4_17 (g4_17 g5_17 g4_9 PBULK p4_17 p5_17 p4_9 VDD VSS) BCircle
               BCircle4_18 (g4_18 g5_18 g4_10 PBULK p4_18 p5_18 p4_10 VDD VSS) BCircle
               BCircle4_19 (g4_19 g5_19 g4_11 PBULK p4_19 p5_19 p4_11 VDD VSS) BCircle
               BCircle4_20 (g4_20 g5_20 g4_12 PBULK p4_20 p5_20 p4_12 VDD VSS) BCircle
               BCircle4_21 (g4_21 g5_21 g4_13 PBULK p4_21 p5_21 p4_13 VDD VSS) BCircle
               BCircle4_22 (g4_22 g5_22 g4_14 PBULK p4_22 p5_22 p4_14 VDD VSS) BCircle
               BCircle4_23 (g4_23 g5_23 g4_15 PBULK p4_23 p5_23 p4_15 VDD VSS) BCircle
               BCircle4_24 (g4_24 g5_24 g4_16 PBULK p4_24 p5_24 p4_16 VDD VSS) BCircle
               BCircle4_25 (g4_25 g5_25 g4_17 PBULK p4_25 p5_25 p4_17 VDD VSS) BCircle
               BCircle4_26 (g4_26 g5_26 g4_18 PBULK p4_26 p5_26 p4_18 VDD VSS) BCircle
               BCircle4_27 (g4_27 g5_27 g4_19 PBULK p4_27 p5_27 p4_19 VDD VSS) BCircle
               BCircle4_28 (g4_28 g5_28 g4_20 PBULK p4_28 p5_28 p4_20 VDD VSS) BCircle
               BCircle4_29 (g4_29 g5_29 g4_21 PBULK p4_29 p5_29 p4_21 VDD VSS) BCircle
               BCircle4_30 (g4_30 g5_30 g4_22 PBULK p4_30 p5_30 p4_22 VDD VSS) BCircle
               BCircle4_31 (g4_31 g5_31 g4_23 PBULK p4_31 p5_31 p4_23 VDD VSS) BCircle

               WSquare3_0 (g3_0 g4_0 PBULK p3_0 p4_0 VDD VSS) WSquare
               WSquare3_1 (g3_1 g4_1 PBULK p3_1 p4_1 VDD VSS) WSquare
               WSquare3_2 (g3_2 g4_2 PBULK p3_2 p4_2 VDD VSS) WSquare
               WSquare3_3 (g3_3 g4_3 PBULK p3_3 p4_3 VDD VSS) WSquare
               BSquare3_4 (g3_4 g4_4 g3_0 PBULK p3_4 p4_4 p3_0 VDD VSS) BSquare
               BSquare3_5 (g3_5 g4_5 g3_1 PBULK p3_5 p4_5 p3_1 VDD VSS) BSquare
               BSquare3_6 (g3_6 g4_6 g3_2 PBULK p3_6 p4_6 p3_2 VDD VSS) BSquare
               BSquare3_7 (g3_7 g4_7 g3_3 PBULK p3_7 p4_7 p3_3 VDD VSS) BSquare
               BSquare3_8 (g3_8 g4_8 g3_4 PBULK p3_8 p4_8 p3_4 VDD VSS) BSquare
               BSquare3_9 (g3_9 g4_9 g3_5 PBULK p3_9 p4_9 p3_5 VDD VSS) BSquare
               BSquare3_10 (g3_10 g4_10 g3_6 PBULK p3_10 p4_10 p3_6 VDD VSS) BSquare
               BSquare3_11 (g3_11 g4_11 g3_7 PBULK p3_11 p4_11 p3_7 VDD VSS) BSquare
               BSquare3_12 (g3_12 g4_12 g3_8 PBULK p3_12 p4_12 p3_8 VDD VSS) BSquare
               BSquare3_13 (g3_13 g4_13 g3_9 PBULK p3_13 p4_13 p3_9 VDD VSS) BSquare
               BSquare3_14 (g3_14 g4_14 g3_10 PBULK p3_14 p4_14 p3_10 VDD VSS) BSquare
               BSquare3_15 (g3_15 g4_15 g3_11 PBULK p3_15 p4_15 p3_11 VDD VSS) BSquare
               BSquare3_16 (g3_16 g4_16 g3_12 PBULK p3_16 p4_16 p3_12 VDD VSS) BSquare
               BSquare3_17 (g3_17 g4_17 g3_13 PBULK p3_17 p4_17 p3_13 VDD VSS) BSquare
               BSquare3_18 (g3_18 g4_18 g3_14 PBULK p3_18 p4_18 p3_14 VDD VSS) BSquare
               BSquare3_19 (g3_19 g4_19 g3_15 PBULK p3_19 p4_19 p3_15 VDD VSS) BSquare
               BSquare3_20 (g3_20 g4_20 g3_16 PBULK p3_20 p4_20 p3_16 VDD VSS) BSquare
               BSquare3_21 (g3_21 g4_21 g3_17 PBULK p3_21 p4_21 p3_17 VDD VSS) BSquare
               BSquare3_22 (g3_22 g4_22 g3_18 PBULK p3_22 p4_22 p3_18 VDD VSS) BSquare
               BSquare3_23 (g3_23 g4_23 g3_19 PBULK p3_23 p4_23 p3_19 VDD VSS) BSquare
               BSquare3_24 (g3_24 g4_24 g3_20 PBULK p3_24 p4_24 p3_20 VDD VSS) BSquare
               BSquare3_25 (g3_25 g4_25 g3_21 PBULK p3_25 p4_25 p3_21 VDD VSS) BSquare
               BSquare3_26 (g3_26 g4_26 g3_22 PBULK p3_26 p4_26 p3_22 VDD VSS) BSquare
               BSquare3_27 (g3_27 g4_27 g3_23 PBULK p3_27 p4_27 p3_23 VDD VSS) BSquare
               BSquare3_28 (g3_28 g4_28 g3_24 PBULK p3_28 p4_28 p3_24 VDD VSS) BSquare
               BSquare3_29 (g3_29 g4_29 g3_25 PBULK p3_29 p4_29 p3_25 VDD VSS) BSquare
               BSquare3_30 (g3_30 g4_30 g3_26 PBULK p3_30 p4_30 p3_26 VDD VSS) BSquare
               BSquare3_31 (g3_31 g4_31 g3_27 PBULK p3_31 p4_31 p3_27 VDD VSS) BSquare

               WSquare2_0 (g2_0 g3_0 PBULK p2_0 p3_0 VDD VSS) WSquare
               WSquare2_1 (g2_1 g3_1 PBULK p2_1 p3_1 VDD VSS) WSquare
               BCircle2_2 (g2_2 g3_2 g2_0 PBULK p2_2 p3_2 p2_0 VDD VSS) BCircle
               BCircle2_3 (g2_3 g3_3 g2_1 PBULK p2_3 p3_3 p2_1 VDD VSS) BCircle
               BCircle2_4 (g2_4 g3_4 g2_2 PBULK p2_4 p3_4 p2_2 VDD VSS) BCircle
               BCircle2_5 (g2_5 g3_5 g2_3 PBULK p2_5 p3_5 p2_3 VDD VSS) BCircle
               BCircle2_6 (g2_6 g3_6 g2_4 PBULK p2_6 p3_6 p2_4 VDD VSS) BCircle
               BCircle2_7 (g2_7 g3_7 g2_5 PBULK p2_7 p3_7 p2_5 VDD VSS) BCircle
               BCircle2_8 (g2_8 g3_8 g2_6 PBULK p2_8 p3_8 p2_6 VDD VSS) BCircle
               BCircle2_9 (g2_9 g3_9 g2_7 PBULK p2_9 p3_9 p2_7 VDD VSS) BCircle
               BCircle2_10 (g2_10 g3_10 g2_8 PBULK p2_10 p3_10 p2_8 VDD VSS) BCircle
               BCircle2_11 (g2_11 g3_11 g2_9 PBULK p2_11 p3_11 p2_9 VDD VSS) BCircle
               BCircle2_12 (g2_12 g3_12 g2_10 PBULK p2_12 p3_12 p2_10 VDD VSS) BCircle
               BCircle2_13 (g2_13 g3_13 g2_11 PBULK p2_13 p3_13 p2_11 VDD VSS) BCircle
               BCircle2_14 (g2_14 g3_14 g2_12 PBULK p2_14 p3_14 p2_12 VDD VSS) BCircle
               BCircle2_15 (g2_15 g3_15 g2_13 PBULK p2_15 p3_15 p2_13 VDD VSS) BCircle
               BCircle2_16 (g2_16 g3_16 g2_14 PBULK p2_16 p3_16 p2_14 VDD VSS) BCircle
               BCircle2_17 (g2_17 g3_17 g2_15 PBULK p2_17 p3_17 p2_15 VDD VSS) BCircle
               BCircle2_18 (g2_18 g3_18 g2_16 PBULK p2_18 p3_18 p2_16 VDD VSS) BCircle
               BCircle2_19 (g2_19 g3_19 g2_17 PBULK p2_19 p3_19 p2_17 VDD VSS) BCircle
               BCircle2_20 (g2_20 g3_20 g2_18 PBULK p2_20 p3_20 p2_18 VDD VSS) BCircle
               BCircle2_21 (g2_21 g3_21 g2_19 PBULK p2_21 p3_21 p2_19 VDD VSS) BCircle
               BCircle2_22 (g2_22 g3_22 g2_20 PBULK p2_22 p3_22 p2_20 VDD VSS) BCircle
               BCircle2_23 (g2_23 g3_23 g2_21 PBULK p2_23 p3_23 p2_21 VDD VSS) BCircle
               BCircle2_24 (g2_24 g3_24 g2_22 PBULK p2_24 p3_24 p2_22 VDD VSS) BCircle
               BCircle2_25 (g2_25 g3_25 g2_23 PBULK p2_25 p3_25 p2_23 VDD VSS) BCircle
               BCircle2_26 (g2_26 g3_26 g2_24 PBULK p2_26 p3_26 p2_24 VDD VSS) BCircle
               BCircle2_27 (g2_27 g3_27 g2_25 PBULK p2_27 p3_27 p2_25 VDD VSS) BCircle
               BCircle2_28 (g2_28 g3_28 g2_26 PBULK p2_28 p3_28 p2_26 VDD VSS) BCircle
               BCircle2_29 (g2_29 g3_29 g2_27 PBULK p2_29 p3_29 p2_27 VDD VSS) BCircle
               BCircle2_30 (g2_30 g3_30 g2_28 PBULK p2_30 p3_30 p2_28 VDD VSS) BCircle
               BCircle2_31 (g2_31 g3_31 g2_29 PBULK p2_31 p3_31 p2_29 VDD VSS) BCircle

               WSquare1_0 (g1_0 g2_0 PBULK p1_0 p2_0 VDD VSS) WSquare
               BSquare1_1 (g1_1 g2_1 g1_0 PBULK p1_1 p2_1 p1_0 VDD VSS) BSquare
               BSquare1_2 (g1_2 g2_2 g1_1 PBULK p1_2 p2_2 p1_1 VDD VSS) BSquare
               BSquare1_3 (g1_3 g2_3 g1_2 PBULK p1_3 p2_3 p1_2 VDD VSS) BSquare
               BSquare1_4 (g1_4 g2_4 g1_3 PBULK p1_4 p2_4 p1_3 VDD VSS) BSquare
               BSquare1_5 (g1_5 g2_5 g1_4 PBULK p1_5 p2_5 p1_4 VDD VSS) BSquare
               BSquare1_6 (g1_6 g2_6 g1_5 PBULK p1_6 p2_6 p1_5 VDD VSS) BSquare
               BSquare1_7 (g1_7 g2_7 g1_6 PBULK p1_7 p2_7 p1_6 VDD VSS) BSquare
               BSquare1_8 (g1_8 g2_8 g1_7 PBULK p1_8 p2_8 p1_7 VDD VSS) BSquare
               BSquare1_9 (g1_9 g2_9 g1_8 PBULK p1_9 p2_9 p1_8 VDD VSS) BSquare
               BSquare1_10 (g1_10 g2_10 g1_9 PBULK p1_10 p2_10 p1_9 VDD VSS) BSquare
               BSquare1_11 (g1_11 g2_11 g1_10 PBULK p1_11 p2_11 p1_10 VDD VSS) BSquare
               BSquare1_12 (g1_12 g2_12 g1_11 PBULK p1_12 p2_12 p1_11 VDD VSS) BSquare
               BSquare1_13 (g1_13 g2_13 g1_12 PBULK p1_13 p2_13 p1_12 VDD VSS) BSquare
               BSquare1_14 (g1_14 g2_14 g1_13 PBULK p1_14 p2_14 p1_13 VDD VSS) BSquare
               BSquare1_15 (g1_15 g2_15 g1_14 PBULK p1_15 p2_15 p1_14 VDD VSS) BSquare
               BSquare1_16 (g1_16 g2_16 g1_15 PBULK p1_16 p2_16 p1_15 VDD VSS) BSquare
               BSquare1_17 (g1_17 g2_17 g1_16 PBULK p1_17 p2_17 p1_16 VDD VSS) BSquare
               BSquare1_18 (g1_18 g2_18 g1_17 PBULK p1_18 p2_18 p1_17 VDD VSS) BSquare
               BSquare1_19 (g1_19 g2_19 g1_18 PBULK p1_19 p2_19 p1_18 VDD VSS) BSquare
               BSquare1_20 (g1_20 g2_20 g1_19 PBULK p1_20 p2_20 p1_19 VDD VSS) BSquare
               BSquare1_21 (g1_21 g2_21 g1_20 PBULK p1_21 p2_21 p1_20 VDD VSS) BSquare
               BSquare1_22 (g1_22 g2_22 g1_21 PBULK p1_22 p2_22 p1_21 VDD VSS) BSquare
               BSquare1_23 (g1_23 g2_23 g1_22 PBULK p1_23 p2_23 p1_22 VDD VSS) BSquare
               BSquare1_24 (g1_24 g2_24 g1_23 PBULK p1_24 p2_24 p1_23 VDD VSS) BSquare
               BSquare1_25 (g1_25 g2_25 g1_24 PBULK p1_25 p2_25 p1_24 VDD VSS) BSquare
               BSquare1_26 (g1_26 g2_26 g1_25 PBULK p1_26 p2_26 p1_25 VDD VSS) BSquare
               BSquare1_27 (g1_27 g2_27 g1_26 PBULK p1_27 p2_27 p1_26 VDD VSS) BSquare
               BSquare1_28 (g1_28 g2_28 g1_27 PBULK p1_28 p2_28 p1_27 VDD VSS) BSquare
               BSquare1_29 (g1_29 g2_29 g1_28 PBULK p1_29 p2_29 p1_28 VDD VSS) BSquare
               BSquare1_30 (g1_30 g2_30 g1_29 PBULK p1_30 p2_30 p1_29 VDD VSS) BSquare
               BSquare1_31 (g1_31 g2_31 g1_30 PBULK p1_31 p2_31 p1_30 VDD VSS) BSquare

               BTriangle0_0 (a0 b0 g1_0 PBULK p1_0 VDD VSS) BTriangle
               BTriangle0_1 (a1 b1 g1_1 PBULK p1_1 VDD VSS) BTriangle
               BTriangle0_2 (a2 b2 g1_2 PBULK p1_2 VDD VSS) BTriangle
               BTriangle0_3 (a3 b3 g1_3 PBULK p1_3 VDD VSS) BTriangle
               BTriangle0_4 (a4 b4 g1_4 PBULK p1_4 VDD VSS) BTriangle
               BTriangle0_5 (a5 b5 g1_5 PBULK p1_5 VDD VSS) BTriangle
               BTriangle0_6 (a6 b6 g1_6 PBULK p1_6 VDD VSS) BTriangle
               BTriangle0_7 (a7 b7 g1_7 PBULK p1_7 VDD VSS) BTriangle
               BTriangle0_8 (a8 b8 g1_8 PBULK p1_8 VDD VSS) BTriangle
               BTriangle0_9 (a9 b9 g1_9 PBULK p1_9 VDD VSS) BTriangle
               BTriangle0_10 (a10 b10 g1_10 PBULK p1_10 VDD VSS) BTriangle
               BTriangle0_11 (a11 b11 g1_11 PBULK p1_11 VDD VSS) BTriangle
               BTriangle0_12 (a12 b12 g1_12 PBULK p1_12 VDD VSS) BTriangle
               BTriangle0_13 (a13 b13 g1_13 PBULK p1_13 VDD VSS) BTriangle
               BTriangle0_14 (a14 b14 g1_14 PBULK p1_14 VDD VSS) BTriangle
               BTriangle0_15 (a15 b15 g1_15 PBULK p1_15 VDD VSS) BTriangle
               BTriangle0_16 (a16 b16 g1_16 PBULK p1_16 VDD VSS) BTriangle
               BTriangle0_17 (a17 b17 g1_17 PBULK p1_17 VDD VSS) BTriangle
               BTriangle0_18 (a18 b18 g1_18 PBULK p1_18 VDD VSS) BTriangle
               BTriangle0_19 (a19 b19 g1_19 PBULK p1_19 VDD VSS) BTriangle
               BTriangle0_20 (a20 b20 g1_20 PBULK p1_20 VDD VSS) BTriangle
               BTriangle0_21 (a21 b21 g1_21 PBULK p1_21 VDD VSS) BTriangle
               BTriangle0_22 (a22 b22 g1_22 PBULK p1_22 VDD VSS) BTriangle
               BTriangle0_23 (a23 b23 g1_23 PBULK p1_23 VDD VSS) BTriangle
               BTriangle0_24 (a24 b24 g1_24 PBULK p1_24 VDD VSS) BTriangle
               BTriangle0_25 (a25 b25 g1_25 PBULK p1_25 VDD VSS) BTriangle
               BTriangle0_26 (a26 b26 g1_26 PBULK p1_26 VDD VSS) BTriangle
               BTriangle0_27 (a27 b27 g1_27 PBULK p1_27 VDD VSS) BTriangle
               BTriangle0_28 (a28 b28 g1_28 PBULK p1_28 VDD VSS) BTriangle
               BTriangle0_29 (a29 b29 g1_29 PBULK p1_29 VDD VSS) BTriangle
               BTriangle0_30 (a30 b30 g1_30 PBULK p1_30 VDD VSS) BTriangle
               BTriangle0_31 (a31 b31 g1_31 PBULK p1_31 VDD VSS) BTriangle

               ends ADDER


               // Library name: PDVS
               // Cell name: XNOR
               // View name: schematic
               subckt XNOR A B PBULK VDD VSS Z
               MP4 (Z A net63 PBULK) PFET w=(wdef*8) l=ldef  \
                       
               MP5 (net63 B VDD PBULK) PFET w=(wdef*8) l=ldef  \
                       
               MP3 (Z net48 VDD PBULK) PFET w=(wdef*4) l=ldef  \
                       
               MP2 (net48 A VDD PBULK) PFET w=(wdef*2) l=ldef  \
                       
               MP1 (net48 B VDD PBULK) PFET w=(wdef*2) l=ldef  \
                       
               MN3 (net35 net48 VSS VSS) NFET w=(wdef*4) l=ldef  \
                       
               MN5 (Z B net35 VSS) NFET w=(wdef*4) l=ldef  \
                       
               MN4 (Z A net35 VSS) NFET w=(wdef*4) l=ldef  \
                       
               MN1 (net32 B VSS VSS) NFET w=(wdef*2) l=ldef  \
                       
               MN2 (net48 A net32 VSS) NFET w=(wdef*2) l=ldef  \
                       
               ends XNOR
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: XOR
               // View name: schematic
               subckt XOR A B PBULK VDD VSS Z
               MP2 (net19 A net3 PBULK) PFET w=(wdef*4) l=ldef  \
                       
               MP3 (net9 net19 VDD PBULK) PFET w=(wdef*8) l=ldef  \
                       
               MP4 (Z B net9 PBULK) PFET w=(wdef*8) l=ldef  \
                       
               MP5 (Z A net9 PBULK) PFET w=(wdef*8) l=ldef  \
                       
               MP1 (net3 B VDD PBULK) PFET w=(wdef*4) l=ldef  \
                       
               MN3 (Z net19 VSS VSS) NFET w=(wdef*2) l=ldef  \
                       
               MN5 (Z B net30 VSS) NFET w=(wdef*4) l=ldef  \
                       
               MN1 (net19 B VSS VSS) NFET w=wdef l=ldef  \
                       
               MN2 (net19 A VSS VSS) NFET w=wdef l=ldef  \
                       
               MN4 (net30 A VSS VSS) NFET w=(wdef*4) l=ldef  \
                       
               ends XOR
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: Sum
               // View name: schematic
               subckt Sum C G P S VDD VSS PBULK
                   I1 (net12 C PBULK VDD VSS S) XNOR
                   I0 (P G PBULK VDD VSS net12) XOR
               ends Sum
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: FirstSum
               // View name: schematic
               subckt FirstSum G P S VDD VSS PBULK
                   I0 (G P PBULK VDD VSS S) XOR
               ends FirstSum
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: WTriangle
               // View name: schematic
               subckt WTriangle C G PBULK VDD VSS
               MP0 (C G VDD PBULK) PFET w=(wdef*4) ld=ldef  \
                       
               MN0 (C G VSS VSS) NFET w=(wdef*2) l=ldef  
               ends WTriangle
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: AND2
               // View name: schematic
               subckt AND2 A B PBULK VDD VSS Z
               M2 (Z net29 VDD PBULK) PFET w=(wdef*4) l=ldef  \
                       
               M1 (net29 B VDD PBULK) PFET w=(wdef*2) l=ldef  \
                       
               M0 (net29 A VDD PBULK) PFET w=(wdef*2) l=ldef  \
                       
               M5 (Z net29 VSS VSS) NFET w=(wdef*2) l=ldef  \
                       
               M4 (net14 A VSS VSS) NFET w=(wdef*2) l=ldef  \
                       
               M3 (net29 B net14 VSS) NFET w=(wdef*2) l=ldef  \
                       
               ends AND2
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: NOR
               // View name: schematic
               subckt NOR A B PBULK VDD VSS Z
               MP0 (net55 A VDD PBULK) PFET w=(wdef*8) l=ldef  \
                       
               MP1 (Z B net55 PBULK) PFET w=(wdef*8) l=ldef  \
                       
               MN0 (Z A VSS VSS) NFET w=(wdef*2) l=ldef  
               MN1 (Z B VSS VSS) NFET w=(wdef*2) l=ldef  
               ends NOR
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: NAND
               // View name: schematic
               subckt NAND A B PBULK VDD VSS Z
               MP0 (Z A VDD PBULK) PFET w=(wdef*4) l=ldef  \
                       
               MP1 (Z B VDD PBULK) PFET w=(wdef*4) l=ldef  \
                       
               MN0 (net15 A VSS VSS) NFET w=(wdef*4) l=ldef  \
                       
               MN1 (Z B net15 VSS) NFET w=(wdef*4) l=ldef  \
                       
               ends NAND
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: BCircle
               // View name: schematic
               subckt BCircle GL GOUT GR PBULK PL POUT PR VDD VSS
                   I11 (PL GR PBULK VDD VSS net33) AND2
                   I10 (net33 GL PBULK VDD VSS GOUT) NOR
                   I12 (PR PL PBULK VDD VSS POUT) NAND
               ends BCircle
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: OR
               // View name: schematic
               subckt OR A B PBULK VDD VSS Z
               MP0 (net028 A VDD PBULK) PFET w=(wdef*4) l=ldef  
                       
               MP1 (net023 B net028 PBULK) PFET w=(wdef*4) l=ldef  
                       
               MP2 (Z net023 VDD PBULK) PFET w=(wdef*4) l=ldef  
                       
               MN0 (net023 A VSS VSS) NFET w=wdef l=ldef  
                       
               MN2 (Z net023 VSS VSS) NFET w=(wdef*2) l=ldef  
                       
               MN1 (net023 B VSS VSS) NFET w=wdef l=ldef  
                       
               ends OR
               // End of subcircuit definition.
	       

	       
               // Library name: PDVS
               // Cell name: BSquare
               // View name: schematic
               subckt BSquare GL GOUT GR PBULK PL POUT PR VDD VSS
                   I8 (net27 GL PBULK VDD VSS GOUT) NAND
                   I7 (PL GR PBULK VDD VSS net27) OR
                   I9 (PR PL PBULK VDD VSS POUT) NOR
               ends BSquare
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: INV
               // View name: schematic
               subckt INV A PBULK VDD VSS Z
               MP0 (Z A VDD PBULK) PFET w=(wdef*4) l=ldef 
                       
               MN0 (Z A VSS VSS) NFET w=(wdef*2) l=ldef  
               ends INV
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: WSquare
               // View name: schematic
               subckt WSquare GIN GOUT PBULK PIN POUT VDD VSS
                   I2 (GIN PBULK VDD VSS GOUT) INV
                   I3 (PIN PBULK VDD VSS POUT) INV
               ends WSquare
               // End of subcircuit definition.

               // Library name: PDVS
               // Cell name: BTriangle
               // View name: schematic
               subckt BTriangle A B GOUT PBULK POUT VDD VSS
                   I3 (A B PBULK VDD VSS POUT) NOR
                   I2 (A B PBULK VDD VSS GOUT) NAND
               ends BTriangle

// End of subcircuit definition.
               
              
             